shikra: Enable Iris video codec (DT + driver support)#671
shikra: Enable Iris video codec (DT + driver support)#671gouravk-qualcomm wants to merge 19 commits into
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PR #671 — validate-patchPR: #671
Final Summary
Recommendation: Fix tag ordering before merge. Move all Link tags to appear after the final Signed-off-by tag in each commit message.
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PR #671 — checker-log-analyzerPR: #671
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Merge Check Failed: No CR Numbers Found Error: No Change Request numbers were found. Please add Change Request numbers to your pull request description in the format CRs-Fixed: 12345 or link GitHub issues that are associated with Change Requests. |
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UBWC configuration is not applicable to all SoCs. Add a check to avoid configuring UBWC during sys init on unsupported platforms. Link: https://lore.kernel.org/all/20260515-iris-ar50lt-v3-1-df3846e74347@oss.qualcomm.com/ Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> Reviewed-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com> Reviewed-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
…bilities The raw formats supported by Iris were previously advertised unconditionally, assuming UBWC support on all platforms. However, some platforms do not support UBWC which results in incorrect format capability exposure. Use the UBWC configuration provided by the platform to dynamically filter raw formats at runtime. If UBWC is not supported, UBWC-based formats are omitted from the advertised capability list, while linear formats remain available. Link: https://lore.kernel.org/all/20260515-iris-ar50lt-v3-2-df3846e74347@oss.qualcomm.com/ Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> Reviewed-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com> Reviewed-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
The set_preset_registers sequence is currently shared across all supported devices. Starting with Qualcomm QCM2290 (AR50LT), the register programming would differ. Move set_preset_register into a vpu_op to allow per-device customization. This change prepares the driver for upcoming hardware variants. No functional change so far for existing devices. Link: https://lore.kernel.org/all/20260515-iris-ar50lt-v3-3-df3846e74347@oss.qualcomm.com/ Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> Reviewed-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com> Reviewed-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
The interrupt_init sequence is currently shared across all supported devices. Starting with Qualcomm QCM2290 (AR50LT), the register programming would differ. Move interrupt_init into a vpu_op to allow per-device customization. This change prepares the driver for upcoming hardware variants. No functional change so far for existing devices. Link: https://lore.kernel.org/all/20260515-iris-ar50lt-v3-4-df3846e74347@oss.qualcomm.com/ Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> Reviewed-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
On AR50LT platforms AbsolutelyPerfectRouting (ARP) needs to be disabled so firmware can configure the ARP internal buffer as non-secure for encoder usage. In preparation of adding support for AR50LT platforms, add an optional disable_arp callback to the VPU ops and invoke it from core init and resume paths. No functional change for existing platforms. Link: https://lore.kernel.org/all/20260515-iris-ar50lt-v3-5-df3846e74347@oss.qualcomm.com/ Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> Reviewed-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com> Reviewed-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
… mask For AR50LT core, the value of WRAPPER_INTR_STATUS_A2HWD_BMASK differs from the currently supported VPUs. In preparation for adding AR50LT support in subsequent patches, introduce a platform data field, wd_intr_mask, to capture the watchdog interrupt bitmask per platform. Link: https://lore.kernel.org/all/20260515-iris-ar50lt-v3-6-df3846e74347@oss.qualcomm.com/ Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
…voting AR50LT require explicit instantaneous bandwidth (IB) voting in addition to average bandwidth (AB) when configuring interconnect QoS. This requirement is due to QSB (Qualcomm System Bus) 128b to QNS ( Qualcomm Network Switch) 256b conversion at video noc in AR50LT which is not needed for other IRIS cores. In preparation of adding support for AR50LT core, introduce platform-configurable IB multiplier and enable IB voting for all SoCs. Existing platforms default to IB == AB, while AR50LT requires 2x peak bandwidth. Link: https://lore.kernel.org/all/20260515-iris-ar50lt-v3-8-df3846e74347@oss.qualcomm.com/ Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> Reviewed-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
AR50Lt doesn't support HFI_PROPERTY_PARAM_WORK_ROUTE. Tables for AR50LT won't have corresponding entry in the capability tables. Let iris_set_pipe() silently skip propgramming the property if there is no corresponding capability. Link: https://lore.kernel.org/all/20260515-iris-ar50lt-v3-8-df3846e74347@oss.qualcomm.com/ Reviewed-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com> Reviewed-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Add power sequence for ar5lt core. Add register handling for ar50lt by hooking up vpu op with ar50lt specific implemtation or resue from earlier generation wherever feasible. Link: https://lore.kernel.org/all/20260515-iris-ar50lt-v3-9-df3846e74347@oss.qualcomm.com/ Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
AR50Lt with the Gen1 firmware requires host to read HFI_PROPERTY_CONFIG_BUFFER_REQUIREMENTS property, otherwie it doesn't update internal data and fails the HFI_CMD_SESSION_LOAD_RESOURCES command. Implement minimal support for querying the properties from the firmware. Link: https://lore.kernel.org/all/20260515-iris-ar50lt-v3-10-df3846e74347@oss.qualcomm.com/ Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Upon receiving data for HFI_PROPERTY_CONFIG_BUFFER_REQUIREMENTS the driver should update buffer sizes and counts from the received data. Implement corresponding functionality updating buffers data. This will be used for upcoming support of AR50Lt platforms with Gen1 firmware. Link: https://lore.kernel.org/all/20260515-iris-ar50lt-v3-11-df3846e74347@oss.qualcomm.com/ Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Port support for the AR50Lt video codec core (present for example on the Agatti platform) to the Iris driver. Unlike more recent cores this generation doesn't have the PIPE property (as it always has only one pipe). Also, unlike newer platforms, buffer sizes are requested from the firmware instead of being calculated by the driver. Link: https://lore.kernel.org/all/20260515-iris-ar50lt-v3-12-df3846e74347@oss.qualcomm.com/ Co-developed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Introduces AR50LT buffer size calculation for both encoder and decoder. Reuse the buffer size calculation which are common, while adding the AR50LT specific ones separately. Link: https://lore.kernel.org/all/20260515-iris-ar50lt-v3-13-df3846e74347@oss.qualcomm.com/ Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Agatti platform is using HFI Gen1 firmware, which is considered to be legacy firmware branch. Follow the example of the SC7280 platform and extend the driver with supporting both HFI Gen1 and Gen2 firmwares for this platform. Like HFI Gen1 this firmware doesn't have PIPE property (but unlike Gen1 buffer sizes are calculated on the driver side). Link: https://lore.kernel.org/all/20260515-iris-ar50lt-v3-14-df3846e74347@oss.qualcomm.com/ Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
…RIS is enabled" This reverts commit 37a0a28. Signed-off-by: Gourav Kumar <gouravk@qti.qualcomm.com>
As the Iris driver now supports the QCM2290 hardware too, there is a race between Venus and Iris drivers on binding to the corresponding device. Follow the approach used by other platforms and skip QCM2290 in the Venus driver if Iris is enabled. Link: https://lore.kernel.org/all/20260515-iris-ar50lt-v3-15-df3846e74347@oss.qualcomm.com/ Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
Mark inst_fw_cap_sm8250_dec as a const array, the data is read-only. Link: https://lore.kernel.org/all/20260515-iris-ar50lt-v3-16-df3846e74347@oss.qualcomm.com/ Suggested-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Add the Iris video codec device tree node for the Shikra platform. Shikra reuses the QCM2290-class video hardware and programming model. The video node is added to describe the Iris based video decoder encoder block, allowing the media driver to probe and initialize the hardware. Link: https://lore.kernel.org/all/20260609-shikra_vpu-v1-2-3a32bb38b080@oss.qualcomm.com/ Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
Enable video en/decoder on the Shikra EVK board. Link: https://lore.kernel.org/all/20260609-shikra_vpu-v1-3-3a32bb38b080@oss.qualcomm.com/ Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Test Matrix
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This PR enables Iris video codec support for the Qualcomm Shikra platform by
adding the required DT nodes and integrating the corresponding driver changes.
CRs-Fixed: 4568062
qli-2.0 GA Critical Fix